Digital CMOS ICs

Course Code:

EV-501

Objective:

To provide knowledge of Digital CMOS ICs

Description:

Process flow and masking steps for MOS and CMOS technologies, Lambda based design rules- Electrical behavior of MOS transistors; Latch up in CMOS technology.
Layer properties of various conducting layers in MOS technology (diffusion, poly-silicon and metal): Sheet resistance, relative capacitance.
Fundamental time constant (τ) for a technology.
Design and analysis of NMOS (enhancement and depletion) and CMOS inverters; rationing of transistor size, logic threshold, logic low voltage level, rise and fall of delays.
Design of basic gates in NMOS technology; CMOS logic design styles: static CMOS logic (AND, NOR gates), complex gates, domino logic, pseudo NMOS logic, clocked CMOS (C2 MOS) logic.
Structured logic design: programmable arrays.
Design of latches and flip-flops, static memory cell and dynamic memory cell.
Sense amplifier- necessity, design, influence of Sense Amplifier on cell Architecture.
MOS scaling theory and scaling of interconnection.

Text/References:

1. Wireless Communication and Networking by John W. Mark, Weihua Zhuang.
2. Wireless Adhoc Networks by M. Ilyas, CRC Press
3. Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis
and Design, McGraw-Hill, 1998.
4. Neil H.E.Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 1998.
5. Rabaey et al., Digital Integrated Circuits, Pearson India, 2002.
6. K. Martin, Digital Integrated circuit design, Oxford University press, 2001.
7. A.Mukherji, Introduction to nMOS and CMOS VLSI system design, Prentice Hall Inc., 1986.
8. C.Mead and L.Conway, Introduction to VLSI systems, Addison Wesley, 1986.
9. Glasser and Dobberpuhl, Design and analysis of VLSI circuits, Addison Wesley, 1985.



Last updated on: Monday, June 27, 2011